发明名称 Chip size package and manufacturing method thereof
摘要 A removal area EL is provided as a first dicing line in a dicing area, coat materials 6' and 7' are put on the flanks of the removal area, a resin layer R is formed, and a dicing blade narrower than the width of the removal area EL is used to fully cut on a second dicing line, whereby the interface exposed by the first dicing can be coated and protected.
申请公布号 US6326701(B1) 申请公布日期 2001.12.04
申请号 US20000512481 申请日期 2000.02.23
申请人 SANYO ELECTRIC CO., LTD. 发明人 SHINOGI HIROYUKI;TAKAI NOBUYUKI;TOKUSHIGE RYOJI;TAKAO YUKIHIRO;KITAGAWA KATSUHIKO
分类号 H01L23/31;(IPC1-7):H01L21/76 主分类号 H01L23/31
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