发明名称 |
Method of fabricating integrated circuits |
摘要 |
A method of fabricating integrated circuits. An oxide layer and a patterned dummy gate layer are formed on a substrate. The patterned dummy gate layer is used as an implantation mask in a first ion implantation step to form a source/drain in the substrate. After performing a step to reduce the width of the patterned dummy gate layer, the narrower patterned dummy gate layer is used as an implantation mask in a second ion implantation step to form a source/drain extension in the substrate. A planarized dielectric layer is formed over the substrate; after which the dummy gate layer and the underlying oxide layer are removed to form an opening inside the dielectric layer. A gate dielectric layer and a metal gate are formed inside the opening.
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申请公布号 |
US6323112(B1) |
申请公布日期 |
2001.11.27 |
申请号 |
US20000498329 |
申请日期 |
2000.02.04 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LOU CHINE-GIE |
分类号 |
H01L21/28;H01L21/336;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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