发明名称 |
Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester |
摘要 |
A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the test pin terminal. A data shifter shifts read data from the DRAM core which operates according to the internal test clock signal in a test mode by N clock cycles (N is an integer of at least 0 determined by column latency) of the internal test clock signal to output the read data from the test pin terminals in synchronization with the external clock test signal.
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申请公布号 |
US2001040829(A1) |
申请公布日期 |
2001.11.15 |
申请号 |
US20010810503 |
申请日期 |
2001.03.19 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ARIMOTO KAZUTAMI;SHIMANO HIROKI;DOSAKA KATSUMI |
分类号 |
G11C11/401;G11C29/02;G11C29/48;H01L21/822;H01L27/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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