| 发明名称 |
Memory cell configuration |
| 摘要 |
The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.
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| 申请公布号 |
US2001036101(A1) |
申请公布日期 |
2001.11.01 |
| 申请号 |
US20010854259 |
申请日期 |
2001.05.10 |
| 申请人 |
SCHLOSSER TILL;KRAUTSCHNEIDER WOLFGANG;HOFMANN FRANZ;HANEDER THOMAS-PETER |
发明人 |
SCHLOSSER TILL;KRAUTSCHNEIDER WOLFGANG;HOFMANN FRANZ;HANEDER THOMAS-PETER |
| 分类号 |
G11C11/22;H01L21/8246;H01L21/8247;H01L27/105;H01L29/788;H01L29/792;(IPC1-7):G11C11/22 |
主分类号 |
G11C11/22 |
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