| 摘要 |
PURPOSE:To relieve the load of software control on a master set side attended with the increase in serial data by synchronizing a signal requiring synchronization with plural synchronization pulses at a slave set side. CONSTITUTION:The serial data processing circuit receiving plural synchronization pulses P1, P2 whose phases differ from each other and provided to a slave set to which serial data including data to be synchronized with any of the plural synchronization pulses P1, P2 is provided with 1st and 2nd latch circuit sections 2, 3 provided to the synchronization pulses P1, P2 from the master set and latching input data by the synchronization pulses P1, P2 to send the data to be synchronized with the other synchronization pulse P2 among the data latched by the 1st latch circuit 2 with the synchronization pulse P1 to the 2nd latch circuit 3 latched by the synchronization pulse P2. |
