发明名称 |
LOGIC GATE BASED ON INVALIDATED LATCHING |
摘要 |
PROBLEM TO BE SOLVED: To provide a pre-charge circuit that latches an output based on a logical input for transition from a pre-charge state to an evaluation state. SOLUTION: This invention provides the pre-charge circuit that has a 1st pre-charged node, a 2nd pre-charged node and a latch device. The 1st pre- charged node is charged to a high level for a pre-charge state. The 1st pre- charged node is discharged to a low level or remains to be charged at a high level in response to the transition from the pre-charge state to the evaluation state. The 2nd pre-charged node in the evaluation state has a value based on d a value of the 1st pre-charged node at the transition of the circuit to the evaluation state. The latch device is connected to the 2nd pre-charged node and latches the value in the evaluation state. The 1st pre-charged node does not affect this value by the latch device when the circuit is once sufficiently transited to the evaluation state.
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申请公布号 |
JP2001292057(A) |
申请公布日期 |
2001.10.19 |
申请号 |
JP20010045408 |
申请日期 |
2001.02.21 |
申请人 |
HEWLETT PACKARD CO <HP> |
发明人 |
NAFFZIGER SAMUEL D;JAEN JEI DESAI;RAY JAMES RIIDORINGAA |
分类号 |
H03K19/096;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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