| 摘要 |
<p>A semiconductor storage device operating according to SRAM specifications in which normal access is not delayed by the effect of refresh and the memory cycle can be shortened as compared with conventional one. An ATD circuit (4) is subjected to variation of address (Address) and generates a one-shot pulse in an address variation detection signal (ATD) after an address skew period. In response to a write request, a write enable signal (/WE) is caused to fall during the address skew period. Write or read is started at the rise of the one-shot pulse. When write is performed, late write is performed, using an address and data provided when write is requested immediately before. Subsequently, refresh is performed within a period from the fall of the one-shot pulse and to the end of the address skew period of the next memory cycle. For the late write performed in response to the next write request, an address and data are taken into register circuits (3, 12) at the rise of the write enable signal (/WE).</p> |
