Semiconductor memory device allowing reduction in power consumption during standby

摘要

A synchronous signal generating circuit 100 includes a delay circuit 110 which receives and delays an external clock signal Ext.CLK by a predetermined time for issuing the same, a phase comparator 120 which compares an output of the delay circuit 110 with a phase of the external clock signal Ext.CLK, a variable constant current source circuit 140 which varies in a digital manner a value of a constant current supplied to an output node 140a based on a result of comparison by the phase comparator 120, and a delay control circuit 150 which adjusts a degree of delay by the delay circuit 110 in accordance with the value of the constant current supplied to the output node 140a. The degree of delay by the delay circuit 110 is controlled in accordance with the value of the constant current which varies linearly in accordance with the result of phase comparison.