发明名称 |
High performance load/store functional unit and data cache |
摘要 |
A load/store functional unit and a corresponding data cache of a superscalar microprocessor is disclosed. The load/store functional unit includes a plurality of reservation station entries which are accessed in parallel and which are coupled to the data cache in parallel. The load/store functional unit also includes a store buffer circuit having a plurality of store buffer entries. The store buffer entries are organized to provide a first in first out buffer where the outputs from less significant entries of the buffer are provided as inputs to more significant entries of the buffer. |
申请公布号 |
US6298423(B1) |
申请公布日期 |
2001.10.02 |
申请号 |
US19960703299 |
申请日期 |
1996.08.26 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
JOHNSON WILLIAM M.;WITT DAVID B.;CHINNAKONDA MURALI |
分类号 |
G06F12/08;G06F9/312;G06F9/38;(IPC1-7):G06F12/02 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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