摘要 |
A programmable DMA controller (110) that uses an instruction set dedicated t o moving data efficiently over a bus (108), comprising a program memory (228), a program counter (226), a FIFO memory (222), a bus buffer (224), registers, a n accumulator, and an ALU (220). The DMA controller instruction set comprises the following instructions: load, move, add, subtract, branch on zero, branc h on not zero, lock, and interrupt. Another DMA controller embodiment uses a SIMD processor. In operation, a CPU downloads DMA programs to the DMA controller. The DMA controller stores these programs in its program memory. The CPU signals the DMA to begin a DMA transfer operation. The ALU and associated devices execute the program instructions to perform the desired D MA transfer. The DMA controller then sends an interrupt to the CPU to indicate the DMA transfer is complete.
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