| 摘要 |
PURPOSE: A data input buffer circuit is provided, which reduces a power consumption because the data input buffer does not operate till a write command after an active command. CONSTITUTION: The data input buffer circuit(20) compares/amplifies a difference between an external data(DIN) and a reference voltage(VREF), and comprises the first PMOS transistor(21) where a power supply voltage(VDD) is connected to a source and a buffer enable signal is connected to a gate, and the second PMOS transistor(22) whose source is connected to a drain of the first PMOS transistor and whose gate is connected with a drain. And the circuit also comprises the third PMOS transistor(23) whose source is connected to the drain of the first PMOS transistor and whose gate is connected to the gate of the second PMOS transistor. The fourth NMOS transistor(24) has a drain connected to the drain of the second PMOS transistor and a gate connected to the reference voltage and a source connected to a ground voltage(VSS). And the fifth NMOS transistor(25) has a drain connected to the drain of the third PMOS transistor and a gate connected to an external data(DIN) and a source connected to the ground voltage. The circuit further includes an inverter(26) serially connected to the drain of the fifth NMOS transistor.
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