| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory device capable of reducing an erroneous cache in the case of competition of cache blocks and to easily presume a state of a cache memory from the outside and a high performance data processing system using the same. SOLUTION: The cache memory device 5 with two caches having no relation of inclusion is prepared between a processor 1 and a low order memory 9 such as an L2 memory and a storage device. In one cache (naked cache) 6, data transfer is explicitly controlled by software and in the other cache (cache for erroneous cache) 7, data to cause the erroneous cache is transferred. Thus, a comprehensive drawn image of the cache is provided to the software and erroneous cache penalty when the data transfer is beyond explicit control by the software is minimized.
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