| 摘要 |
PROBLEM TO BE SOLVED: To protect an input MOS transistor without decreasing the operating speed in ordinary signal processing for the input of a second high level, limiting the operating condition of a circuit and decreasing the operating speed at the time of second high level input in a semiconductor integrated circuit to which the second level further higher than an ordinary high level is inputted. SOLUTION: This circuit is provided with a high potential detecting circuit 8 for detecting that an input IN is the second high level, a NAND gate circuit 50 for inputting the output of a NOR gate circuit 10 and an output S1 of the high potential detecting circuit, and pMOS transistor TP4 for pulling up an output point t N1 of the NOR gate circuit to a power supply voltage VDD. When the input IN is the second high level, the output S1 of the high potential detecting circuit becomes 'L' and an output OUT does not depend on the output of the NOR gate circuit 10. Then, the output point N1 of the NOR gate circuit 10 is directly pulled up to the power supply voltage by the output S1 of the high potential detecting circuit.
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