Multiprocessor system bus with a data-less castout mechanism

摘要

A method and apparatus for casting out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. In response to a castout write request from a cache memory to a non-inclusive lower-level cache memory within a cache memory hierarchy, the data transfer is aborted if the lower-level cache memory already has a copy of the data of the castout write. The coherency state of the lower-level cache memory is then updated, if necessary.