Write pipelining with global ordering in mulipath multiprocessor systems with a single input-output device, uses bus adapters controlling access to an operation queue which is used to control operation sequence

摘要

The pipeline has bus adapters (115,120) each connected to a CPU (105,110). A queue controlled by the bus adapter retains operations sent by the CPUs. A controller coupled to the queue generates signals from the operation data. An interconnection device (135) coupled to the bus adapters transmits these signals to a receiving device (140) which sends an acknowledgment to the sending CPU.