发明名称 TEST SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To shorten extremely long test time of a test in wafer stage using a prober, where individual semiconductor chips are tested sequentially in conventional IC inspection, in which inspection is made both in a wafer stage and in a packaged stage. SOLUTION: A test without using a tester can be made, by constructing test circuits on a probe card or on a wafer in which semiconductor chips to be tested are formed and by electrically connecting the test circuits respectively to the semiconductor chips to be tested for performing the test. In addition, by conducting test in wafer stage in an aging apparatus, it is possible to simplify or omit the test, after being packaged.
申请公布号 JP2001210685(A) 申请公布日期 2001.08.03
申请号 JP20000264193 申请日期 2000.08.31
申请人 HITACHI LTD 发明人 SHIMIZU ISAO;SATO MASAYUKI;FUKIAGE HIROSHI
分类号 G01R1/06;G01R31/28;G01R31/30;G01R31/3183;H01L21/66;(IPC1-7):H01L21/66;G01R31/318 主分类号 G01R1/06
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