| 摘要 |
<p>A co-simulation design system (100) that runs on a host computer system (113) is described that includes a hardware simulator (103) and a processor simulator (107) coupled via an interface mechanism (119). The execution of a user program (109) on a target processor that includes a cache is simulated by executing an analyzed version (111) of the user program (109) on the host computer system (100). The analysis (112) adds timing information (117) to the user program (109) so that the processor simulator (107) provides accurate timing information (110) whenever the processor (107) interacts with the hardware simulator (103). The analysis also adds hooks to the user program (109) such that executing the analyzed user program (111) on the host computer system (113) invokes a cache simulator (121) that simulates operation of the cache.</p> |
