发明名称 |
Dual damascene method for backened metallization using poly stop layers |
摘要 |
A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.
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申请公布号 |
US6262484(B1) |
申请公布日期 |
2001.07.17 |
申请号 |
US19990295812 |
申请日期 |
1999.04.20 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
RANGARAJAN BHARATH;SUBRAMANIAN RAMKUMAR;SINGH BHANWAR |
分类号 |
H01L21/768;(IPC1-7):H01L23/485;H01L23/52;H01L23/532 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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