| 摘要 |
PURPOSE: An apparatus for an interrupt service routine in a system having a cache memory is provided to increase the hit ratio of a cache by storing a command and data used in an interrupt service routine in a special zero standby internal SRAM, and by directly reading the command and the data without passing by a cache memory. CONSTITUTION: A CPU(10) controls a system. A cache memory(30) stores a command and data used in the CPU(10). A cache control unit(20) controls the cache memory(30). A system bus(40) connects the CPU(10), the cache control unit(20), the cache memory(30), a memory control unit(50) and an interrupt control unit(60). A main memory(80) stores the command and the data used in the service routine. The interrupt control unit(60) recognizes an interrupt request signal. A zero standby internal SRAM(70) stores the command and the data used in the service routine. The memory control unit(50) controls an input/output of the command and the data stored in the zero standby internal SRAM(70).
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