发明名称 DIGITAL SIGNAL PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a square sum arithmetic circuit based on a superior ROM system with small ROM capacity for a digital signal processor used for various electrics. SOLUTION: Respective absolute value arithmetic means 1a to 1n generate the absolute values of inputs 1 to (n) and an adder 2 adds up the respective absolute values. Then a ROM 3 calculates the sum squares of vectors by using the sum inputted from the adder 2 as its address value and assigning as a data value the average of all vectors which are equal in the sum of absolute values. The ROM 3 of the digital signal processor which is thus constituted needs to have only a ROM capacity of as large as 2 raised to the (m+n-1)th power. Therefore, the sum of squares of vectors can be computed with ROM capacity which is much smaller than the ROM capacity of a conventional ROM system which is as large as 2 raised to the (m×n)th power. Here, (n) is the number of dimensions of an input vector and (m) is the number of configuration bits of each element.
申请公布号 JP2001185956(A) 申请公布日期 2001.07.06
申请号 JP19990371248 申请日期 1999.12.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIRAIWA MOTOTSUGU;OTOMO HIROSHI
分类号 H03D1/00;(IPC1-7):H03D1/00 主分类号 H03D1/00
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