| 摘要 |
PROBLEM TO BE SOLVED: To save the area of a large-scale macrocell part. SOLUTION: In the macrocell part 1 for a CPU or the like, wiring layers 5 are formed as five layers. Consequently, the margin degree of the formation of an interconnection inside the macrocell part 1 is increased. When a main power-supply potential line 27 and a main ground potential line 28 are arranged inside the region of the macrocell part 1, the area of the semiconductor integrated circuit can be saved. When main power-supply potential lines 27c and main ground potential lines 28c on a fundamental cell region 3 are subdivided as a plurality of lines, the wiring efficiency of an internal interconnection 6 in the fundamental cell region 3 is enhanced. |
