发明名称 MULTILAYERED WIRING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce crosstalk between different layer wiring and improve wiring efficiency. SOLUTION: First and second layer wiring are formed on orthogonal grids 11, 12. Whenθ=arctan(na/mb) is established using first and second layer wiring pitches (a, b) and even number n, m exceeding 2, third and fourth layer wiring are formed on inclined grids 13, 14, so that they can incline in the positive and negativeθdirection against the first layer wiring, respectively. Third and fourth layer wiring pitches (c, d) are C=d=na×mb/ (na)2+(mb)2}1/2. All the intersections of the third and fourth wiring are located at the position where they overlap with the intersections of the orthogonal grids 11, 12. Fifth and sixth layer wiring are formed on coarse orthogonal grids 15, 16 that form a subset of the orthogonal grids 11, 12. Fifth and sixth layer wiring pitches (e, f) are e=na and f=mb, and all the intersections of the fifth and sixth wiring are located at the position where they overlap with the intersections of the inclined girds 13, 14.
申请公布号 JP2001168195(A) 申请公布日期 2001.06.22
申请号 JP19990345715 申请日期 1999.12.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YASUI TAKUYA;TOYONAGA MASAHIKO
分类号 H01L21/82;G06F17/50;(IPC1-7):H01L21/82 主分类号 H01L21/82
代理机构 代理人
主权项
地址