| 摘要 |
PURPOSE: A redundancy circuit of a semiconductor memory device where a number of banks share one repair cell array is provided to reduce layout area without a mis-operation. CONSTITUTION: A repair cell array comprises an array of a number of 4 cell units comprising four repair cells. Each 4 unit cell inputs or outputs data to/from the repair cell through direct data buses(DB0,DB1,DB2,DB3) in response to bank address signal(Yi_Bank0,Yi_Bank1,Yi_Bank2,Yi_Bank3) and repair row address signals(RWL0,RWL1,RWL2,RWL3) and column address signals(Yi0,Yi1,Yi2,Yi3) corresponding to each bank. The 4 unit cell comprises four repair cells and an input part controlling a path between the repair cell and the data bus. The repair cell includes a latch storing data and NMOS transistors connecting the latch with the data bus through a source-drain path connected serially each other.
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