| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit that limits an operation of a frequency comparator circuit with its output in the case of a lock range of the phase comparator circuit and stably reads data by conducting phase lock even in the case of a recovered data pulse with much clock jitter. SOLUTION: The PLL circuit A is provided with a frequency comparator circuit 1 that detects a phase difference based on a frequency difference between a recovered data pulse and an output frequency of a VCO 7, a phase comparator circuit 2 that detects a phase difference between the recovered data pulse with the VCO clock, a selection circuit 3 that selectively outputs an output of the frequency comparator circuit 1, a 2nd change pump circuit 5 that increases/ decreases an output voltage based on the output of the phase comparator circuit 2, a 1st change pump circuit 4 that increases/decreases an output voltage based on the output of the selection circuit 3, a loop filter 6 that eliminates an undesired component included in outputs of the 1st charge pump circuit 4 and the 2nd charge pump circuit 5, and the VCO 7 that oscillates a frequency corresponding to the output of the loop filter 6. |
