发明名称 Digital signal processor with management of memory allocation between program and data memory
摘要 In a memory system, a plurality of memories having different bit widths from each other and each including at least one block and a plurality of buses are provided. At least one selector is connected between the block and at least two of the buses and selectively connects the block to one of the at least two buses.
申请公布号 US6240497(B1) 申请公布日期 2001.05.29
申请号 US19980084803 申请日期 1998.05.26
申请人 NEC CORPORATION 发明人 YAGI MINORU
分类号 G06F12/06;G06F12/04;(IPC1-7):G06F12/10 主分类号 G06F12/06
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