| 摘要 |
PURPOSE: A VSB(Vestigial Sideband) convolutional deinterleaver for correcting decoding delay error is provided to correct error data by inhibiting the address designation of a memory during a synchronizing signal interval in which the error data is generated. CONSTITUTION: A write address generator(10) delays an input synchronizing signal by a decoding delay time to generate a write address, thereby correcting the decoding delay error. A read address generator(20) generates a memory read address disabled during an output synchronizing signal is output, thereby correcting the decoding delay error. A MUX(30) multiplexes addresses generated from the write address generator(10) and read address generator(20). A memory(40) has a memory area of (£M*£(B-1)B/2|+1|+1 segment size), records interleaving data in the write address output from the MUX(30) and reads data from the read address output from the MUX to deinterleave the data.
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