| 发明名称 |
MANUFACTURING METHOD OF GATE STRUCTURE |
| 摘要 |
PROBLEM TO BE SOLVED: To provide the manufacturing method of gate structure where resistance is low even if a gate electrode is not made to be high and the height of the electrode can be suppressed. SOLUTION: An etching processing using vapor hydrofluoric acid is executed and a TEOS oxide film 11 comprising the prescribed concentration of impurity is selectively removed. Then, a metal film is formed in an area surrounded by a TEOS oxide film 12 and polysilicon 3.
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| 申请公布号 |
JP2001127288(A) |
申请公布日期 |
2001.05.11 |
| 申请号 |
JP19990306667 |
申请日期 |
1999.10.28 |
| 申请人 |
MITSUBISHI ELECTRIC CORP |
发明人 |
SHIRAHATA MASAYOSHI;KITAZAWA MASASHI;OTA KAZUNOBU |
| 分类号 |
H01L21/302;H01L21/28;H01L21/3065;H01L21/336;H01L29/49;H01L29/78;(IPC1-7):H01L29/78;H01L21/306 |
主分类号 |
H01L21/302 |
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