| 摘要 |
PURPOSE: The high-speed fourier converter is provided to process transmission data at high speed in real time by arranging each function block in parallel, and by processing the data in a pipeline mode. CONSTITUTION: An address control unit(100) outputs an address signal which writes and reads data to a memory by a control signal of a central control unit(105). A dual port memory unit(130) reads and outputs the data by the address signal. A coefficient memory unit(120) reads and outputs a coefficient value of a complex number. A butterfly control unit(110) outputs a control signal. The first and the second arithmetic logic unit(140,145) simultaneously process an addition and a subtraction by the control signal. The first register(150) temporarily stores data processed from the first arithmetic logic unit(140). The second register(155) temporarily stores data processed from the second arithmetic logic unit(145). The first multiplier(162) gets an approval for a real value from the first register(150). The second multiplier(164) gets an approval for an imaginary value from the second register(155). The third multiplier(166) gets an approval for a real value from the first register(150). The fourth multiplier(168) gets an approval for an imaginary value from the second register(155). The first adder(170) writes an upper real in the dual port memory unit(130) through the first data bus. The second adder(175) writes an upper imaginary in the dual port memory unit(130) through the first data bus.
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