| 发明名称 |
Method and apparatus for performing cache accesses |
| 摘要 |
A method and apparatus for performing cache accesses. A comparator is coupled to a cache and a lookup parity bit line to perform error detection. |
| 申请公布号 |
US6226763(B1) |
申请公布日期 |
2001.05.01 |
| 申请号 |
US19980126029 |
申请日期 |
1998.07.29 |
| 申请人 |
INTEL CORPORATION |
发明人 |
FU JOHN WAI CHEONG;MULLA DEAN AHMAD |
| 分类号 |
G06F11/10;G06F12/08;(IPC1-7):H02H3/05 |
主分类号 |
G06F11/10 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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