| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit which faithfully makes a PLL response to jitter included in an input clock by using a phase frequency comparator manufactured at a low production cost. SOLUTION: The PLL circuit is provided with a voltage controlled oscillator(VCO) 11, a phase comparison part 15, a loop filter 10, and a counter 12 used as a frequency divider. The phase comparison part 15 is the phase frequency comparator. The phase comparison part 15 is provided with a phase (frequency) comparator 5 which compares the phase difference between an input clock S1 and a frequency divided clock S2 and a phase (frequency) comparator 7 which compares the phase difference between the input clock S1 and a frequency divided clock S3 which has been delayed in a delay circuit 4 by a prescribed time. The delay circuit 4 shifts phases of dead zones in the vicinities of phase centers of two phase comparators 5 and 7. An output S4 of the phase comparator 5 and an output S5 of the phase comparator 7 are synthesized by a synthesizing circuit 9 to supply a phase comparison signal S8 having no dead zones to the VCO 11. |
