发明名称 Speicheranordnung
摘要 The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and driven via word and bit lines. Said memory device comprises two metallised sheets through which the bit line is led and between which the memory cell stacked capacitor is arranged.
申请公布号 DE19948571(A1) 申请公布日期 2001.04.19
申请号 DE19991048571 申请日期 1999.10.08
申请人 INFINEON TECHNOLOGIES AG 发明人 HOENIGSCHMID, HEINZ;BRAUN, GEORG
分类号 G11C5/10;H01L21/8242;H01L27/108;(IPC1-7):H01L27/108;G11C11/413 主分类号 G11C5/10
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