| 摘要 |
A computer system is described including a CPU core, a memory device storing non-cacheable data, and a bus interface unit (BIU) coupled between the CPU core and the memory device. The CPU core accesses the memory device via the BIU. The BIU includes a stream read buffer, and the system includes logic to determine when to enter a stream read buffer mode. includes a stream read buffer. Following at least one transaction accessing the non-cacheable data within the memory device, the BIU obtains a portion of the non-cacheable data from the memory device, and stores the portion within the stream read buffer. For example, the memory device may include multiple storage locations for storing the non-cacheable data, and the storage locations may have consecutive addresses. Following the least one transaction accessing the non-cacheable data, the BIU may obtain the contents of multiple, consecutively-addressed storage locations of the memory device, and store the contents within the stream read buffer. The stream read buffer may thus be used to store large blocks of non-cacheable data from the memory device. As the CPU core is able to access the stream read buffer faster than the memory device, the efficiencies of data transactions directed to the memory device may be increased. The CPU core may include circuitry for monitoring transactions accessing the non-cacheable data within the memory device.
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