发明名称 CHARACTERISTIC ESTIMATION CIRCUIT FOR SEMICONDUCTOR WAFER AND ESTIMATING METHOD THEREOF
摘要 PURPOSE: A characteristic estimation method for a semiconductor wafer is provided to easily destruct or disable a characteristic estimation circuit, by installing the characteristic estimation circuit in a scribe region between semiconductor chips or in a characteristic estimation region having the same size as the semiconductor chip. CONSTITUTION: A proper voltage is applied to a gate voltage control pad(P8,P9,P10) to turn off a depletion-type metal-oxide-semiconductor(MOS) transistor(501,502,503). A probe is placed on the pad to estimate the characteristic of a dummy device after the proper voltage is applied to the gate voltage control pad. A fuse(F8,F9,F10) connected to the gate of the depletion-type MOS transistor is cut after the dummy device is estimated.
申请公布号 KR20010029742(A) 申请公布日期 2001.04.16
申请号 KR20000028308 申请日期 2000.05.25
申请人 NEC CORPORATION 发明人 YAMAGAMI MINORU
分类号 H01L27/04;H01L21/66;H01L21/82;H01L21/822;H01L23/544;(IPC1-7):H01L21/66 主分类号 H01L27/04
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