发明名称 BIT LINE CONTACT HAVING STABLE CONTACT RESISTANCE AND MANUFACTURING METHOD THEREOF
摘要 PURPOSE: A method for manufacturing a bit line contact is provided to simultaneously guarantee stable contact resistance in regions having different contact characteristics, by forming a titanium silicide layer in a bit line contact formed on a polysilicon pad while not forming the titanium silicide layer in a bit line contact formed on a gate. CONSTITUTION: A plurality of the first and second transistors have gate electrodes composed of polysilicon/tungsten silicide on a semiconductor substrate(100) including a cell array region and a peripheral circuit region. The first interlayer dielectric is formed on the substrate including the plurality of the first and second transistors. The first interlayer dielectric is etched to form the first and second openings for forming a pad exposing the substrate between the first and second transistors. Polysilicon is formed inside the first and second openings to manufacture the first and second conductive pads. A titanium silicide layer(230) is selectively formed on the first and second conductive pads. The second interlayer dielectric is formed on the resultant structure. The second interlayer dielectric is etched to form the first, second and third bit line contact holes which expose the silicide layer on the first and second conductive pad and the tungsten silicide layer of the second transistor. A barrier metal layer(240,290) and a bit line metal layer(300) are formed on the bit line contact hole and the second interlayer dielectric.
申请公布号 KR20010028057(A) 申请公布日期 2001.04.06
申请号 KR19990040116 申请日期 1999.09.17
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JUN, YUN SU
分类号 H01L27/108;(IPC1-7):H01L27/108 主分类号 H01L27/108
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