| 摘要 |
<p>The invention concerns a method for locating faulty elements in an integrated circuit. The method consists: in modelling the integrated circuit in the form of a tree of nodes and directed arcs; measuring at various nodes of the circuit by applying a testing sequence in the circuit input; recursively determining the nodes to be tested on the basis of the previously performed tests. Each new testing node is such that the number of its ancestors is substantially equal to the number of its descendants.</p> |
