| 摘要 |
PROBLEM TO BE SOLVED: To provide a D flip-flop whose occupied area in an integrated circuit can be much more reduced. SOLUTION: The D flip-flop consists of series connection of two clocked CMOS inverters and 2-input 2-output clocked CMOS inverters in place of two clocked CMOS static latch circuits each consisting of a MOS inverter, which is simultaneously turned on/off synchronously with biphase clock pulses that are inverted from each other. The 2-input 2-output clocked CMOPS inverter is an inverter where P-MOS and N-MOS transistors(TRs) 23, 24 that are simultaneously turned on/off synchronously with biphase clock pulses that are inverted from each other are connected between two bias sources and a circuit consisting of parallel connection of CMOS inverters 21, 22.
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