Semiconductor memory device having test mode

摘要

In an output buffer of a DRAM, a level shifter outputs a step-up potential responsively when an internal data signal goes low or a test mode signature goes high. An N-channel MOS transistor is rendered conductive in response to the step-up potential from the level shifter, and sets a data input terminal to a power supply potential. The internal data signal and the test mode signature share the level shifter and the N-channel MOS transistor, and hence the layout area can be small and a high-level test mode signature can be output.