| 摘要 |
A fabrication method for a capacitor is proposed, beginning with a semiconductor substrate having a bit line and a planarized first dielectric layer formed thereon. A first silicon nitride layer is formed on the first dielectric layer, followed by forming in sequence a second dielectric layer and a second silicon nitride layer on the first silicon nitride layer. A photolithography and etching process is performed to form an opening in the second dielectric layer and the second silicon nitride layer. A conducting spacer is formed on a sidewall of the opening. With the spacer serving as a mask, the first silicon nitride layer and the first dielectric layer are etched to form a terminal contact opening. A conducting layer is then formed to cover the second silicon nitride layer and to fill the terminal contact opening, while the conducting layer on the second silicon nitride layer is removed by etching back. The second silicon nitride layer and the second dielectric layer are removed to expose a part of the conducting layer. A hemispherical grain layer is coated on the exposed surface of the conducting layer to complete manufacture of a lower electrode, while the lower electrode is covered by a dielectric film and an upper electrode to complete manufacture of the capacitor.
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