Semiconductor memory device using a relatively low-speed clock frequency and capable of latching a row address and a column address with one clock signal and performing a page operation

摘要

A semiconductor memory device includes a memory cell array, a plurality of word lines selectively activated by a row address signal from the outside, a plurality of bit lines selected by a column address signal from the outside, and sense amplifiers connected to the bit lines. The device further includes a row address latch circuit for latching the row address signal by using, as a trigger, a first edge of a clock signal from the outside, a sense amplifier activating circuit for activating the sense amplifier after a lapse of a given time from the first edge, a column address latch circuit for latching a column address signal by using, as a trigger, a second edge of the clock signal occurring after the first edge, and a precharge signal generating circuit for generating a precharge signal for precharging the bit lines after a lapse of a given time from the second edge.