发明名称 CODING CIRCUIT AND METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a coding circuit that suppresses occurrence of long consecutive same bits, without significantly increasing a bit error rate at recovery of a signal, and to provide its method. SOLUTION: This coding circuit applies GS(guided scrambling) coding to an arbitrary data series to generate a code series, where run length larger than (k) (k is a natural number) is produced with a probability of P (P≪1). When there is a run length larger than the (k), a run length detector detects the run length and a bit inverter inverts a bit '0' into a bit '1' at the midpoint of the run length, to attain NRZI(non-return to zero inversion) modulation.
申请公布号 JP2001044842(A) 申请公布日期 2001.02.16
申请号 JP19990215269 申请日期 1999.07.29
申请人 SANYO ELECTRIC CO LTD 发明人 KUNIHAZAMA AKIOMI
分类号 H03M7/14;(IPC1-7):H03M7/14 主分类号 H03M7/14
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