CHIP SIZE STACK PACKAGE AND MANUFACTURE THEREFOR

摘要

PROBLEM TO BE SOLVED: To provide a chip size stack package capable of eliminating a signal interference and shortening a signal transmitting path. SOLUTION: A chip size stack package includes: a top and a bottom semiconductor chip 20 arranged with their bonding-pad 21 forming surfaces opposed to each other; insulating layers 30 applied to the bonding-pad forming surfaces of the respective semiconductor chips 20; metal traces 40 deposited on the respective insulating layers 30 and electrically connected to the bonding pads 21; solder balls for electrically connecting the respective metal traces 40; terminals connected to the metal traces 40 and to be connected to the outside; and a sealing agent 90 for molding the side of the whole members such that the terminals to be connected to the outside are exposed from the sides.