| 摘要 |
A computer-implemented method and computer program product or software tool for converting a timing graph produced by a static timing engine into a timing diagram and vice versa may be integrated with a static timing analysis tool or may be a stand-alone product. The timing graph is represented by a data structure having nodes that correspond to actual circuit nodes of a circuit simulated by the timing engine and arcs connecting the nodes that correspond to temporal relationships between points on the timing diagram waveforms, such as points at which state transitions occur. To convert a timing graph to a timing diagram, the data structure is traversed from node to node. State transitions are extracted from each node, and temporal relationships between the signals are extracted from each arc. A graphical representation of the timing diagram is then displayed. Alternatively, the timing diagram is output in a suitable file format, such as Timing Diagram Markup Language (TDML). The steps can be reversed to convert a timing diagram into a timing graph.
|
