发明名称 Method of manufacturing salicide layer
摘要 A method of manufacturing a salicide layer is described. A substrate having a memory region and a logic circuit region is provided, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second source/drain region. A first salicide layer is formed on the second gate structure and the second source/drain region in the logic circuit region. A dielectric layer is formed over the substrate. A portion of the dielectric layer is removed to expose the first gate structure and the first salicide layer above the second gate structure. A second salicide layer is formed on the first and the second gate structure.
申请公布号 US6177319(B1) 申请公布日期 2001.01.23
申请号 US19990345435 申请日期 1999.07.01
申请人 UNITED MICROELECTRONICS CORP. 发明人 CHEN SHU-JEN
分类号 H01L21/8234;H01L21/8242;(IPC1-7):H01L21/823 主分类号 H01L21/8234
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