发明名称 |
Memory device and video image processing apparatus using the same |
摘要 |
A memory device in which a plurality of data can be read out by giving one address and a plurality of data can be read out without adding more address lines is provided, and therefore, the circuit integration is not degraded. The memory device includes: m memory array banks, each including row and column address decoders; a first circuit for receiving one address and generating m row addresses and n column addresses by shifting the one address by a predetermined value for each of the m row and n column addresses; and a second circuit for inputting each of the generated m row and n column addresses to the corresponding row and column address decoders of the m memory array banks.
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申请公布号 |
US6172687(B1) |
申请公布日期 |
2001.01.09 |
申请号 |
US19980044165 |
申请日期 |
1998.03.19 |
申请人 |
SEGA ENTERPRISES, LTD. |
发明人 |
KITAMURA KENYA;YAGI HIROSHI;YASUI KEISUKE |
分类号 |
G11C11/401;G06F12/02;G06F12/06;G06T1/60;G06T11/20;G06T15/00;G09G5/395;G11C8/00;G11C8/02;(IPC1-7):G06F12/06 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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