发明名称 MULTILAYER WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To electrically connect a multilayer wiring board efficiently having laminated parallel interconnections to a high-density semiconductor element, and to reduce the number of laminated layers. SOLUTION: This multilayer wiring board comprises, below a mounting region M of a semiconductor element D, a line wiring layer, and a strip line section. The line wiring layer consists of a line conductor C2 for connecting an upper conductor layer C1 to the element D by a first group of through-conductors T1. The strip line section consists of a lower conductor layer C3. Around the line wiring layer and the strip line section, the multilayer wiring board is also provided with a parallel wiring section, which is formed by connecting a first wiring line L1 to a second wiring line L2 by a second group of through-conductors T2. The line L1 consists of a group of parallel wiring lines having intersecting points with the region M, the parallel wiring lines being formed within the same plane as that of the line wiring layer and extending toward the intersecting points in regions so segmented as to have substantially the same central angle with each other by two to four lines. The second wiring layer L2 consists of a group of parallel wiring lines which are orthogonal to the first layer L1 in the respective segmented regions. Furthermore, the element D is connected to the layer L1 via the line wiring layer.
申请公布号 JP2000323600(A) 申请公布日期 2000.11.24
申请号 JP19990134783 申请日期 1999.05.14
申请人 KYOCERA CORP 发明人 NOMOTO MASARU;TAKEDA SHIGETO;KABUMOTO MASANAO;NABE YOSHIHIRO
分类号 H01L23/12;(IPC1-7):H01L23/12 主分类号 H01L23/12
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