发明名称 DROPOUT RESISTANT PHASE-LOCKED LOOP
摘要 <p>Data signal dropout may cause loss of synchronization between the data signal and a data clock. A dropout resistant system for generating the data clock synchronized to the data signal includes a phase-locked loop. The phase-locked loop outputs the data clock having frequency and phase based on phase difference between the data signal and the data clock. The phase-locked loop holds constant the data clock frequency and minimizes phase shift during periods when an indication of the data signal quality drops beneath a threshold level.</p>
申请公布号 WO2000060806(A2) 申请公布日期 2000.10.12
申请号 US2000040043 申请日期 2000.03.31
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