| 摘要 |
<p>A pointer generation circuit, in accordance with the invention, includes a clock for providing a clock cycle, and a shift register with a plurality of latches for storing data bits. A first latch receives a flag bit upon a first clock cycle of the clock. A switch transfers the flag bit to the shift register on the first clock cycle. The switch connects a last latch to the first latch after the flag bit is transferred to the shift register. The flag bit is transferred to a next latch, wherein the next latch for the last latch is the first latch, at each consecutive clock cycle thereby generating pointer signals in accordance with the clock cycle and the data bits stored in the latches. <IMAGE></p> |
