| 摘要 |
PROBLEM TO BE SOLVED: To accelerate the operating speed of an information processing memory by successively performing read access to plural addresses, which are simultaneously or continuously issued by a cache memory, and performing read access for reading remaining data later. SOLUTION: When a CPU 10 performs miss hits simultaneously or continuously to plural cache lines within four in a cache memory 12 and the cache memory 12 simultaneously or continuously issues the read requests of data for plural cache lines within four, first of all, a synchronous dynamic random access memory(SDRAM) controller 14 successively performs read access to plural addresses within four, which are simultaneously continuously issued by the cache memory 12, in an SDRAM 13. Thus, data acquired by the CPU 10 before are first acquired. Afterwards, read access is performed for reading the remaining data.
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