| 摘要 |
A memory device includes a base memory with a defective memory cell. A read circuit with a serial output port and parallel input ports is connected to the base memory. The read circuit converts parallel read data received at the parallel input ports to a first serial data stream, which is applied to the serial output port. The first serial data stream includes a faulty bit corresponding to the defective memory cell. A spare memory stores a spare bit corresponding to the defective memory cell. A bit insertion circuit is connected to the spare memory and the serial output port of the read circuit. The bit insertion circuit substitutes the faulty bit value of the first serial data stream with the spare bit.
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