| 摘要 |
PURPOSE: An apparatus for arbitrating a memory access is provided to make it possible to sequentially process memory access requests that happens at the same time, by determining a search time period separatedly for each processor. CONSTITUTION: A divider(300) receives a clock signal applied from an AND gate(301) as an internal clock signal(CLKin), and outputs divided clock signals(CLK1,CLK2). An OR gate(304) receives signals(B_CLK1,B_CLK2) as inverted signals of the clocks(CLK1,CLK2), a signal(BR1) applied from a DMA(Direct Memory Access) controller, and thereby outputs a signal(BR1-1). An OR gate(305) receives the signals(B_CLK1,CLK2) and a signal from the DMA controller, and thereby outputs a signal(BR2-1). An AND gate(303) receives the signals(BR1-1,BR2-1). An OR gate(302) receives a signal(B_BGACK), as an inverted signal of a signal(BGACK) from the DMA controller, and an output of the AND gate(303), and thereby generates a signal(BR). An OR gate(306) receives the signal(BR1-1) and a signal(BG) from a processor, and then outputs a signal(BG1) for allowing the DMA controller to use a bus. An OR gate(307) receives the signals(BR2-1,BG), and then outputs a signal(BG2).
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